1. Field of the Present Invention
The present invention generally relates to the field of semiconductor devices and more particularly to a multi-chip module in which power supply degradation is minimized by reducing the length of the metallization layer interconnects required to provide power to the device circuits.
2. History of Related Art
Semiconductor manufacturers have developed single and multi-chip modules (SCMs and MCMs) to provide efficient packages for housing semiconductor devices having a large number of connections. In a chip stack MCM, two or more devices or die are stacked on top of each other and enclosed within a single plastic oF ceramic package. A processor chip, for example, may be stacked on top of a memory chip. Depending upon the implementation, MCM packaging permits a large number of die-to-die interconnections.
In a conventional stacked MCM implementation, the backside of a first die is attached to the active surface of a second die, where the active surface refers to the surface into which transistors and other active devices are fabricated and on top of which metallization layers are produce. A stacked MCM implementation requires some form of wire bond for die-to-die or inter-die connections to make the physical connection from the active surface of the first die to the active surface of the second die. Because wire bonding requires a minimum pad size to achieve adequate reliability, the stacked MCM design places a limit on the number of die-to-die connections possible.
A flip chip MCM design, in which the active surfaces of the first and second die are in contact with each other, greatly increases the number of die to die connections possible by permitting 4C connections to each other. Referring to FIG 1, a flip chip MCM 100 is depicted. In the depicted embodiment, MCM 100 includes a first die 104 and a second die 106 enclosed within a plastic or ceramic package 102. The active surface 105 of first die 104 faces the active surface 107 of second die 106 to enable, die-to-die connections between the die pair via a plurality of controlled collapse chip connections (C4) identified in FIG. 1 by reference numeral 108. External connections to the die pair with a conventional bond pad attach in which a wire 112 connects a bond pad 110 of second die 106 with a lead frame 114. The lead frame is connected to an external conductive element such as the ball grid array 116 depicted.
Those familiar with electronic devices in general will appreciate that the circuits of die 104 and 106 require externally supplied power. Because of the physical arrangement of the die in the flip chip stack as illustrated in FIG. 1, externally supplied signals must attach to the periphery of one of the die. Thus, a circuit 111 that is physically located at or near the center of the die must be connected to the externally supplied power signals (i.e., VDD and ground) via a relatively long metallization interconnect 113. It will be further appreciated by those familiar with semiconductor device electronics that the capacitance and resistivity of the metallization interconnects may result in a significant amount of power supply degradation. This is especially true for high-speed devices (i.e., devices operating in excess of 1 GHz). Thus, although the flip chip stack beneficially enables a large number of die-to-die interconnections, the physical arrangement of the die results in a peripherally powered device that may required a large number of long metallization interconnects. The power dissipated in the interconnections can be a limiting factor in the achievable performance of a give design. Thus, it would be desirable implement a multi-chip module that enabled a large number of die-to-die interconnections without that eliminated the long metallization interconnects characteristic of peripherally powered designs.
The problems identified above are in large part addressed by a multi-chip device or module in which a first die is stacked in contact with a second set of die. The die are stacked in a flip chip arrangement in which the active surface of the first die is in close proximity to the active surfaces of each of the second set of die. Die-to-die connections are made using C4connections. The second set of die are laterally displaced from each other. A set of low resistivity signal posts are provided within the lateral separation between adjacent die in the second set of die. These signal posts are connected to externally supplied power signals such as VDD and ground. The power signals are then routed to the circuits within the second set of die over relatively short metallization interconnects. In one embodiment, the multi-chip module includes a ceramic or plastic package that en closed the first and second set of die. The package may further include thermally conductive elements or heat spreaders on each of the surfaces of the package. External connections may be made to the module through a set of BGA elements that are positioned around the perimeter of t he module. In one embodiment, the BGA elements of the module may be attached to a circuit board over an aperture in the circuit board to provide the ability to attach a heat sink to each of the heat spreaders. In one embodiment, the first die and the second set of die are fabricated with differing technologies where one of the technologies is suitable for fabricating capacitive elements. The first die may comprise a DRAM device while the second set of die comprise portions of a general-purpose microprocessor. In this embodiment, the power signals of the second set of die are connected through one of the capacitor terminals in the first die to provide decoupling of the power signal that is provided to the second set of die.